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3.8.4
Offset Cancellation
The device provides the option to read offset cancelled acceleration data via the SPI by clearing the OC bit in the DEVCFG
register (reference Section 3.1.6.1 ) and in the SPI command (reference Section 4.1 ). A block diagram of the offset cancellation
is shown in Figure 21 , and response parameters are specified in Section 2.4 and in Table 25 .
LPF OUT
Downsampled to 256 μ s
Accumulator
4096 samples
Shift
T1
T Registers updated every 1.049s
T2 T3 T4 T5
T6
OFFTHR NEG
OFF_ERR
1.049s
OFF_ERR
OFFTHR POS
Updated every 1.049s
6 .291s Average
1/8 LSB
Increment 1/4 LSB
1/8 LSB
Decrement 1/4 LSB
Offset Inc/Dec
OFF CORRP
OFF CORRN
OFF_CORR_VALUE
OC OUT
Alignment
Correction
Figure 21. Offset Cancellation Block Diagram
In normal operation, the offset cancellation circuit computes a 24,576 sample running average of the acceleration data down-
sampled to 256 μ s. The running average is compared against positive and negative thresholds to determine the offset correction
value that will be applied to the acceleration data.
During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. Ref-
erence Table 25 for offset cancellation timing information during startup and normal operation. The offset cancellation startup
phase can also be directly controlled during initialization (ENDINIT = ‘0’) using the OCPHASE[1:0] bits and the OFFCFG_EN bit
in the DEVCTL register, as described in Section 3.1.5.2 and Section 3.1.5.3 .
Table 25. Offset Cancellation Timing Specifications
Phase
Start Time of
Phase
(from POR)
Typical
Time in
Phase (ms)
# of Samples in
Phase
Samples
Averaged
OFF_CORR_VALUE
Update Rate (ms)
Averaging
Period
(ms)
Maximum Averaging Filter
Slew Rate -3dB Frequency
(LSB/s) (Hz)
Start 1
Start 2
Start 3
Normal
t OP
t OP + 524.288
t OP + 1048.576
t OP + 1572.864
524.288
524.288
524.288
—
2048
2048
2048
—
48
384
3072
24576
2.048
16.38
131.1
1049
12.288
98.304
786.432
6291.456
122.1
15.26
1.907
0.2384
36.05
4.506
0.5632
0.07040
When the self test circuitry is active, the offset cancellation block and the offset monitor block are suspended, and the offset
correction value is constant. Once the self test circuitry is disabled, the offset cancellation block remains suspended for the time
t ST_OMB to allow the acceleration output to return to it’s nominal offset.
3.8.5
Offset Monitor
The device provides the option for an offset monitor circuit. The offset monitor circuit is enabled when the OFMON bit in the
DEVCFG register is programmed to a logic ‘1’. The output of the offset cancellation circuit is compared against a high and low
threshold. If the offset correction value exceeds either the OFFTHR POS , or OFFTHR NEG threshold, an Offset Over Range Error
condition is indicated.
The offset correction value update rate is listed in Table 25 : “Maximum Slew Rate”. Because the offset monitor uses this value,
the offset monitor will also update at this rate. The time to indicate an Offset Over Range Error is dependent upon the input signal.
The offset monitor status remains suspended during self test, because the offset monitor is based on the offset cancellation
circuit, which is also suspended during self test. The offset monitor is disabled for 2.1 seconds following reset regardless of the
state of the OFMON bit.
MMA655x
Sensor
Freescale Semiconductor, Inc.
33
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